With the introduction of Thread Director in Alder Lake, Intel has finally delivered a heterogeneous processor architecture capable of fine-grained, dynamic task switching, substantially improving energy efficiency to meet the current demands of the desktop market. However, this astonishing advancement has also brought forth a new tier of challenges that require even more engineering effort.

Producing a general purpose CISC processor for a myriad of potential cloud customers is not an easy and cheap task for Intel. The current state of the x86 instruction set is indeed vast, consisting of thousands of instructions, which continually receive new inclusions. At the same time, the diversification of the product portfolio offered in the cloud provider market has been increasing significantly and has enormous potential for expansion in the coming years. And that makes life for Intel engineers a real nightmare. Whether for commercial, legal or security reasons, it is not possible to Intel to predict every case scenario which some instructions may need to be disabled in the future.

In recent years, multi-chiplet GPU designs have become more and more attractive as monolithic GPUs are reaching the reticle limit and it's becoming ever clearer that Moore's Law has its days numbered. However, there are several problems in determining how to disaggregate a GPU into multiple processor blocks.