Introduction to RISC-V and the ISA Landscape

First of all: RISC-V is and Instruction Set Architecture (ISA). The world of ISAs has been dominated by proprietary designs for decades. To understand the significance of RISC-V, it's crucial to first grasp the historical context of ISAs and their role in computing.

What is ISA?

An Instruction Set Architecture (ISA) is the formal description of how the processor should behave. If a computer were a car, the ISA would be the standardized set of controls - the steering wheel, pedals, and gear shift. Just as any driver who knows these standard controls can operate various car models, any software written for a specific ISA can run on any processor that implements that ISA.

Interfaces in programming languages offer a similar concept. They define an object's behavior without specifying its internal workings, much like an ISA does for a processor. An interface establishes a contract of methods that any implementing class must provide, ensuring consistent behavior across different implementations. Just as any software written for a specific ISA can run on any compatible processor, any code written to work with an interface can interact with any object that implements that interface, regardless of its internal structure.

Key aspects of an ISA include:

• Instruction set: The "vocabulary" of commands the processor understands.

• Data types: The kinds of data the processor can work with.

• Registers: The processor's internal storage locations.

• Memory addressing: How the processor accesses data in memory.

Here the example of short ISA summary:

Moreover Instruction Set is one of the most important properties of a software compilation target. Compilation target determines where and how software can run. When software is compiled, it's converted into machine code for a specific target platform.

e.g. here is the truncated list of targets supported by rust compiler to give you an idea:

$ rustc --print target-list | cut -d'-' -f1 |  uniq                                                                                                                 
aarch64
arm64_32
wasm32
wasm64
x86_64
riscv32gc
riscv32i
riscv32im
riscv32ima
riscv32imac
riscv32imafc
riscv32imc
...

This target-specific compilation ensures that the software can take full advantage of the capabilities of the target system, but it also means that software often needs to be adapted or recompiled to work across different platforms.

*Guess you noticed how many riscv32_xxx targets are there, I will slightly touch that later.

The Rise of Proprietary ISAs

In the early days of computing, various companies developed their own processor architectures and corresponding ISAs. Over time, a few key players emerged as dominant forces:

1. x86: Developed by Intel in the 1970s, the x86 architecture became the standard for personal computers.

2. ARM: Originally developed in the 1980s, ARM (Advanced RISC Machine) gained traction in mobile and embedded devices due to its energy efficiency.

These ISAs became entrenched in the industry. As software was developed for these architectures, it became increasingly difficult for new ISAs to gain a foothold.

This ISAs are proprietary and its problematic because:

1. It limits innovation to the owning company.

2. Other manufacturers must pay licensing fees to use these ISAs.

3. Full specifications may not be publicly available.

4. It creates vendor lock-in for users and businesses.

These proprietary ISAs are distributed through licensing agreements, limiting who can create compatible hardware and software.

Porting software between different ISAs is also challenging and resource-intensive. Each ISA has unique instructions, register structures, and memory models, meaning software optimized for one ISA may perform poorly on another without significant rework. This lack of compatibility leads to fragmentation in the software ecosystem, increased development costs, and reduced software availability across platforms.

RISC-V

Roughly speaking, RISC-V is the Linux of the ISA world. Just as Linux revolutionized operating systems with its open-source model, RISC-V challenges proprietary hegemonia in CPU world by providing a free and open instruction set.

RISC part stands for Reduced Instruction Set Computing (RISC), which means it uses a small, efficient set of core instructions. This approach, combining simplicity with openness, provides a vast field for experimentation and makes it highly extensible. Custom instructions can be easily added without disrupting the main architecture, while its open-source nature allows anyone to use or modify it without fees.

This specific properties accelerate RISC-V popularity growth and make it a good choose for experiments and research, especially in cases where you need to extend or modify Instruction Set for specific usecases.

Remember to the zoo of riscv32_xxx targets from ISAs introduction? This is one of the core strengths of RISC-V: base set is tiny and easily support custom extensions.
Here is the set of standard extensions:

As you can see every letter corresponds to some set of specific operations which are not supported by the base set.

Applications and Popularity

RISC-V adoption has rapidly expanded during past several years from initial applications in IoT and mobile devices to a wide range of sectors.

With more and more demand for domain specific accelerators (DSAs) to achieve cost-effective performance on-chip, it is more and more necessary to tune the design to the needs of the workload required. This is where RISC-V extensibility starts to shine!

Domain Specific Acceleration

DSAs are specialized hardware components engineered to efficiently perform specific types of computations for particular application areas. By tailoring their architecture to specific tasks, DSAs offer substantial improvements in performance and energy efficiency compared to general-purpose processors.

For example we can add specific core to the CPU that is designed specifically to solve certain tasks efficiently (like AI cores in many modern CPUs). Following the methaphour from the introduction while base ISA provide basic car function controls you might want to add rocket engine to your car (just in case). Thus you will need additional controls to use this extension of your car. ISA extension does that for the hardware.

Here the live example:

(A) RISC-V hardware is extended with the addition of PiM based Vector-Matrix Multiplication (VMM) functional unit.

(B) Custom instruction extensions are added to the RISC-V ISA to expose the VMM functionality of the PiM hardware to the programmers.

Vector-Matrix Multiplication is one of the most important types of calculations in AI world, this accelerator is designed to execute efficiently.

The ISA extension to interact with this VMM unit:

(A) vmm stands for vector-matrix multiplication itself

(B) vmm.ld stands for load instruction for PiM accelerator memory

(C) vmm.sd stands for custom store instruction for PiM accelerator memory

Examples of some RISC-V-based DSAs in various domains:

• AI and Machine Learning:

  • Custom vector extensions for efficient matrix operations

  • Specialized neural network inference engines

  • Tensor processing units

• Cryptography:

  • Hardware acceleration for common cryptographic algorithms (AES, SHA, etc.)

  • Post-quantum cryptography accelerators

• Ultra-Low-Power IoT:

  • Flexible word lengths (8-, 16-, 24-, and 32-bit) to optimize power consumption

  • Specialized instructions for sensor data processing

  • Energy-efficient wireless communication protocol accelerators

• Signal Processing:

  • Custom DSP instructions for audio and video processing

  • Software-defined radio (SDR) accelerators

  • 5G and beyond communication system accelerators

zkVMs

Due to properties named above RISC-V quickly become the most popular ISA in the current zkVM space. Its used by Risc0, Succinct’s SP1, Nexus, a16z’s Jolt and others.

Let's use Risc0 as an example to get a bird's-eye view of how it works. The main concept is to utilize a RISC-V virtual machine with corresponding ZK circuits to prove this RISC-V instructions execution. It allows to prove execution of programs written in any high-level language that can target the RISC-V ISA. This approach leverages the extensive ecosystem of RISC-V compilers, including LLVM-based toolchains.

Whole pipeline (simplified) looks as follows: